On-the-Fly Hardware-Accelerated Image Processing System for Target Recognition

Upcoming robotic exploration missions are characterized by constantly increasing spacecraft autonomy requirements. This approach includes the necessity to face new challenging tasks, such as autonomous navigation capabilities, adaptive activity scheduling and on-the-edge data processing. When these scenarios meet small satellite platforms, coming with a plethora of resource constraints, an optimized implementation of computing intensive functionalities is necessary to achieve usable performance. Argotec, an Italian aerospace company, designs and develops its own avionics systems to enable challenging inter-planetary small satellite missions. Within this context, Argotec developed a proprietary implementation of a high-throughput image processing pipeline to support vision-based autonomous navigation and attitude control. The purpose of this paper is to present the functionality and the performance of this system. Recalling the building blocks being in the image processing chain, the paper starts by listing these blocks and their functionalities, discussing the reasoning behind their inclusion. These functionalities include data binning, low-pass filtering for edge smoothing, color depth compression, binarization, luminance histogram generation, and eventually multi-target labeling. The challenges of delivering the required performance, high-enough to sustain on-the-fly processing in couple with state-of-the-art space cameras, are presented through the step-by-step integration in a flash-based space-grade Microsemi RTG4 FPGA. The hardware implementation was intentionally generated to be parametrizable and platform-independent, allowing for operativity extensions, scalability and general portability. The datapath was conceived to keep functionalities as separated black boxes, each one autonomically operating. Every functional element expects processed pixels as input from the previous module and generates outputs for the following one. This solution allowed to succeed in an about 20 times faster SW-implementation running on a 50MHz Space-grade SPARC V8 processor, with a very low resource occupation in the FPGA device. In this context, improvements led to a drastic processor utilization time unloading, leaving additional place for extra tasks during mission control cycle period. The technology is eventually analyzed in the real-life application of the DART/LICIACube autonomous planetary defense mission, proving how the design supports the mission-specific pipeline deployed for the critical NASA mission. The paper includes a final consideration that reflects on how technologies related to autonomous navigation are critical for small satellite platforms, and nowadays this aspect is calling for the need to design and tailor new solutions. This image processing pipeline wants to be an example of how new solution can enable multiple mission scenarios, until now considered prerogative of larger platforms

HACK Modular On-Board Computer for Edge Computing in Micro-Satellites

Argotec HACK OBC offers unprecedent flexibility thanks to its design developed from scratch to be modular and easily reconfigurable. Different standard modules, based on both state-of-the-art SoCs and FPGAs, can be assembled without the need of external harness to face a wide variety of applications, from spacecraft management to hardware acceleration. The design leverages a mix of rad-hard, defense-grade and automotive components carefully selected to enable the execution of demanding edge-computing tasks while ensuring a reliability level significantly higher than standard CubeSat avionics. Each HACK module is designed to be powered by a single +5V DC rail and has standardized thermal and mechanical interfaces, allowing the installation both as single unit or as part of a complex OBC subsystem. The standard configuration, which includes one Core Board and one aXelerator Module, has a volume of about 0.5U and offers unmatched performance and interfaces

The First-Ever Asteroid Fly-By Performed by a CubeSat: Outcomes of the LICIACube Mission

Transported onboard NASA Double Asteroid Redirection Test (in short, DART) spacecraft developed by Johns Hopkins Applied Physics Laboratory (APL), the Italian Space Agency (ASI) Light Italian CubeSat for Imaging of Asteroids (in short, LICIACube) played a crucial role in the homonymous mission that took place in September 2022. Its main purpose has been to document the effects of the intentional impact of DART probe with Dimorphos, the minor-planet moon of the 65803 Didymos asteroid system. Along this first-ever planetary defense mission against Near-Earth Objects (NEOs), LICIACube successfully completed the first-ever asteroid fly-by performed by a CubeSat. With a maximum Earth distance of approximately 14 million km during its operative phase, LICIACube is currently one of the nanosatellites that operated the farthest from our planet in a robotic exploration mission. Once separated from DART, the micro-satellite followed its mothercraft along its approach trajectory: its optical system, composed by two digital cameras, is the core of the Autonomous Attitude Control System which allowed to gather images of the two asteroids during a very fast fly-by. This paper discusses how LICIACube behaved in flight, with a focus on the embedded real-time hardware-accelerated imaging capabilities and the Autonomous Attitude Control System as a whole. These technologies allowed the CubeSat to simultaneously operate its two optical payloads both for tracking and science purposes. During the approximately 5-minute-long fly-by, tracking has been performed using the primary telescopic grayscale camera (LICIACube Explorer Imaging for Asteroid, LEIA) to provide rapid feedback to the satellite Autonomous Attitude Control System controlling its attitude, thus maintaining the pointing towards the target. The telescope was exploited to track the main body (Didymos) during the initial phases of the fly-by, switching then to Dimorphos in the vicinity of the closest approach, which occurred with a distance of about 50km and a relative speed of approximately 7 km/s. On the other hand, the secondary payload allowed to capture and store wide-angle images of DART impact with the asteroid, by means of the secondary RGB camera (LICIACube Unit Key Explorer, LUKE) and with a maximum image acquisition rate of 3 pictures per second. In the first section of this paper, the LICIACube CubeSat System is introduced in the DART mission context. In second place, Argotec\u27s all-in-house HAWK-6 platform upon which LICIACube was built is discussed in detail. Followingly, LICIACube in-flight performances are examined with a focus on the Autonomous Attitude Control System. Mission results are included, with real-time telemetry data collected during operations and images of DART captured before and after the impact with Dimorphos

EuFRATE: European FPGA Radiation-hardened Architecture for Telecommunications

The EuFRATE project aims to research, develop and test radiation-hardening methods for telecommunication payloads deployed for Geostationary-Earth Orbit (GEO) using Commercial-Off-The-Shelf Field Programmable Gate Arrays (FPGAs). This project is conducted by Argotec Group (Italy) with the collaboration of two partners: Politecnico di Torino (Italy) and Technische Universit¨at Dresden (Germany). The idea of the project focuses on high-performance telecommunication algorithms and the design and implementation strategies for connecting an FPGA device into a robust and efficient cluster of multi-FPGA systems. The radiation-hardening techniques currently under development are addressing both device and cluster levels, with redundant datapaths on multiple devices, comparing the results and isolating fatal errors. This paper introduces the current state of the project’s hardware design description, the composition of the FPGA cluster node, the proposed cluster topology, and the radiation hardening techniques. Intermediate stage experimental results of the FPGA communication layer performance and fault detection techniques are presented. Finally, a wide summary of the project’s impact on the scientific community is provided

Characterization of Partial and Run-Time Reconfigurable FPGAs

   FPGA based systems have been heavily used to prototype and test Application Specic Integrated Circuit (ASIC) designs with much lower costs and development time compared to hardwired prototypes. In recentyears, thanks to both the latest technology nodes and a change in the architecture of reconfigurable integrated circuits (from traditional Complex Programmable Logic Device (CPLD) to full-CMOS FPGA), FPGAs have become more popular in embedded systems, both as main computation resources and as hardware accelerators. A new era is beginning for FPGA based systems: the partial run-time reconguration of a FPGA is a feature now available in products already on the market and hardware designers and software developers have to exploit this capability. Previous works show that, when designed properly, a system can improve both its power efficiency and its performance taking advantage of a partial run-time reconfigurable architecture. Unfortunately, taking advantage of run-time reconfigurable hardware is very challenging and there are several problems to face: the reconfiguration overhead is not negligible compared to nowadays CPUs performance,the reconfiguration time is not easily predictable, and the software has to be re-though to work with a time-evolving platform. This thesis project aims to investigate the performance of a modern run-time reconfigurable SoC (a Xilinx Zynq 7020), focusing on the reconfiguration overhead and its predictability, on the achievable speedup, and the trade-off and limits of this kind of platform. Since it is not always obvious when an application (especially a real-time one) is really able to use at its own advantage a partial run-time reconfigurable platform, the data collected during this project could be a valid help for hardware designers that use reconfigurable computing.   FPGA-baserade system har tidigare främst använts för snabb och kostnadseffektiv konstruktion av prototyper vid framtagandet av applikationsspecika integrerade kretsar (ASIC). På senare år har användandet av FPGA:er i inbyggda system för implementation av hårdvaruacceleratorers såväl som huvudsaklig beräkningsenhet ökat. Denna ökning har möjliggjorts mycket tack vare den utveckling som har skett av rekonfigurerbara integrerade kretsar: från de mer traditionella Complex Programmable Logic Devices (CPLD) till helt CMOS-baserade FPGA:er. Nu inleds en ny era för FPGA-baserade system tack vare möjligheten att under körning rekonfigurera delar av FPGA:n genom så kallad partial run-time reconguration(RTR) - en teknik som redan idag finns tillgänglig i produkter på marknaden. Tidigare forskning visar att användandet av en RTR-baserad hårdvaruarkitektur kan ha en positiv effekt med avseende på prestanda såväl som strömförbrukning. Att använda RTR-baserad hårdvara innebär dock flera utmaningar: En ej försumbar rekonfigurationstid måste tas i beaktning, så även den icke-deterministiska exekveringstiden som en rekonfiguration kan innebära. Vidare måste anpassningar av mjukvaran göras för att fungera med en hårdvaruplattform som förändras över tid. Denna uppsats syftar till att undersöka prestandan hos ett modernt RTRbaserat SoC (Xilinx Zynq 7020) med fokus på rekonfigurationstider och dess förutsägbarhet, prestanda ökning, begränsningar samt nödvändiga kompromisser som denna arkitektur innebär. Huruvida en applikation kan dra nytta av en RTR-baserad arkitektur eller inte kan vara svårt att avgöra. Den insamlade datan som presenteras i denna rapport kan dock fungera som stöd för hårdvarukonstruktörer som önskar använda en RTR-baserad plattform